Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
authorEddie Hung <eddie@fpgeh.com>
Fri, 20 Sep 2019 17:00:09 +0000 (10:00 -0700)
committerEddie Hung <eddie@fpgeh.com>
Fri, 20 Sep 2019 17:00:09 +0000 (10:00 -0700)
commited187ef1cf118727a8964e26c36530560f3e37db
tree64d716705836512b1115b74a3dff5015e25c3fe0
parent1844498c5f4f19f77919faf056b165d8b282470e
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
passes/pmgen/Makefile.inc
passes/pmgen/xilinx_dsp.cc
passes/pmgen/xilinx_dsp.pmg
passes/pmgen/xilinx_dsp_cascade.pmg [new file with mode: 0644]