fhdl: arrays (TODO: use correct BV for intermediate signals)
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 9 Jul 2012 13:16:38 +0000 (15:16 +0200)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 9 Jul 2012 13:16:38 +0000 (15:16 +0200)
commited27783a5363cd80ad9409aa8298d40bcf8ed412
treeb3dba927febf2cc47dba56e12f601d0a9924545d
parentc82a468506be54756993281ffa48e7cf5cb17951
fhdl: arrays (TODO: use correct BV for intermediate signals)
examples/basic/arrays.py [new file with mode: 0644]
migen/corelogic/misc.py
migen/fhdl/structure.py
migen/fhdl/tools.py
migen/fhdl/verilog.py