intel: Make the fake packed depth/stencil mappings use a cached temporary.

intel: Make the fake packed depth/stencil mappings use a cached temporary.

Before, we had an uncached read of S8 to untile, then a RMW (so
uncached penalty) of the packed S8Z24 to store the value, then the
consumer would uncached read that once per pixel.  If data was written
to the map, we would then have to uncached read the written data back
out and do the scatter to the tiled S8 buffer (also uncached access
penalties, since WC couldn't actually combine).  So 3 or 5 uncached
accesses per pixel in the ROI (and we we were ignoring the ROI, so it
was the whole image).

Now we get an uncached read of S8 to untile, and an uncached read of
Z.  The consumer gets to do cached accesses.  Then if data was
written, we do streaming Z writes (WC success), and scattered S8
tiling writes (uncached penalty).  So 2 or 3 uncached accesses per
pixel in the ROI.

This should be a performance win, to the extent that anybody is doing
software accesses of packed depth/stencil buffers.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>