bit of a mess being sorted out

bit of a mess being sorted out
1) update to this page was inconsistent: now fixed
   https://libre-soc.org/openpower/sv/bitmanip/
2) power_decoder.py bitsel for minor_22.csv had been set to (1,5) which
   is *only four bits* (LSB0 numbering, python-style) 1 2 3 4
   where what was actually needed was (1,6) to be bits (MSB0) 26..30
3) when converting to "ignore" format (previous: 0b00000 new 000000-)
   and adding the extra bit, (2) messed things up.
   bitsel has now been set to (0,6) which is bits 0 1 2 3 4 5
   aka (MSB0) 26..31 and the four instructions setvl/svremap/svshap/svstep
   set to 10011- and 011001 etc. as appropriate
4) the minor_22.csv entries for both svshape and svremap were set to
   Rc=1 mode which is NOT correct

astoundingly the unit tests all functioned correctly despite the above
errors.  now all corrected, unit test test_caller_setvl.py still functions