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(parent: 0a603b3) | patch
back.rtlil: fix sim-synth mismatch with assigns following switches.
authorwhitequark <whitequark@whitequark.org>
Sat, 3 Aug 2019 13:27:47 +0000 (13:27 +0000)
committerwhitequark <whitequark@whitequark.org>
Sat, 3 Aug 2019 13:27:47 +0000 (13:27 +0000)
commitee03eab52fbcb2b110753d198ffa8f2537f1638a
tree47170037165563df9444ec1541fd773972610cbbtree
parent0a603b3844b8da7ede8857f56a2889eff19f15c6commit | diff
back.rtlil: fix sim-synth mismatch with assigns following switches.

Closes #155.
nmigen/back/rtlil.py diff | blob | history