Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
authorClaire Wolf <clifford@clifford.at>
Thu, 14 May 2020 16:06:18 +0000 (18:06 +0200)
committerGitHub <noreply@github.com>
Thu, 14 May 2020 16:06:18 +0000 (18:06 +0200)
commitee0beb481db09e8faddf22109097649eac04486b
treecb4aedf8d0240326bde38d54875752961252dd20
parent27b7ffc75444583bbecc70e2d7e2e84bc321f2cf
parent004999218f52cd5a1308023a474ee608b842a5b7
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto

 ast: swap range regardless of range_left >= 0
frontends/ast/simplify.cc