Improve Verific error handling, check VHDL static asserts
authorClifford Wolf <clifford@clifford.at>
Wed, 4 Oct 2017 16:56:28 +0000 (18:56 +0200)
committerClifford Wolf <clifford@clifford.at>
Wed, 4 Oct 2017 16:56:28 +0000 (18:56 +0200)
commitee56a887b65e74e44aa6601113f0b477211ccdbc
tree2fcb43ca8966e431c739d6f35fda1750d63120cf
parent3f22f48eeb98eb3407f735a3fd254c49043902e9
Improve Verific error handling, check VHDL static asserts
frontends/verific/verific.cc