i965/fs: Properly precolor payload registers on GEN5 in SIMD16

i965/fs: Properly precolor payload registers on GEN5 in SIMD16

For GEN6 SIMD16 mode, we have to 2-align all the registers, so we only have
the even-numbered ones.  This means that we have to divide the register
number by 2 when we precolor.  This wasn't a problem before because we were
setting up the interference between ra_node registers wrong.  This will be
fixed in the next commit.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>