verilog: user-definable reset and clock
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Fri, 16 Dec 2011 21:25:05 +0000 (22:25 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Fri, 16 Dec 2011 21:25:05 +0000 (22:25 +0100)
commitee6ca729a224b5b67bbfc1843237c0f33dd354ad
treea6524cd82cf8eaf6ef7a1ff3ac4c0e71bb6fdde7
parentc7b9dfc203218a200601ff83acb68f719432a125
verilog: user-definable reset and clock
migen/fhdl/verilog.py