fix dsrd pseudocode for new 3-in 2-out
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 27 Oct 2022 14:47:53 +0000 (15:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 27 Oct 2022 14:47:53 +0000 (15:47 +0100)
commiteea94034582ed7686a6150062e321b46b87c3e1b
tree36cb2481b94c8a095dddb79145e885fdd505817b
parentf21545d3f4bbb6fd27a42790afaa490540e8ed9a
fix dsrd pseudocode for new 3-in 2-out
https://bugs.libre-soc.org/show_bug.cgi?id=937#c16
openpower/isa/svfixedarith.mdwn
src/openpower/test/bigint/bigint_cases.py