python: Don't assume SimObjects live in the global namespace
authorAndreas Sandberg <andreas.sandberg@arm.com>
Fri, 25 Jan 2019 14:26:21 +0000 (14:26 +0000)
committerAndreas Sandberg <andreas.sandberg@arm.com>
Tue, 12 Feb 2019 09:43:00 +0000 (09:43 +0000)
commitef71a987c1987f7543d3bf76ed9e5ce62f4d1daa
treec672aa096c0088820c7ffa341b2d603cef6f66d6
parent9fbfb45e51e657b364334a1c96ba23698d181edb
python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
131 files changed:
src/arch/alpha/AlphaSystem.py
src/arch/alpha/AlphaTLB.py
src/arch/arm/ArmISA.py
src/arch/arm/ArmNativeTrace.py
src/arch/arm/ArmPMU.py
src/arch/arm/ArmSemihosting.py
src/arch/arm/ArmSystem.py
src/arch/arm/ArmTLB.py
src/arch/arm/tracers/TarmacTrace.py
src/arch/mips/MipsSystem.py
src/arch/mips/MipsTLB.py
src/arch/power/PowerTLB.py
src/arch/riscv/RiscvSystem.py
src/arch/riscv/RiscvTLB.py
src/arch/sparc/SparcNativeTrace.py
src/arch/sparc/SparcSystem.py
src/arch/sparc/SparcTLB.py
src/arch/x86/X86LocalApic.py
src/arch/x86/X86NativeTrace.py
src/arch/x86/X86System.py
src/arch/x86/X86TLB.py
src/base/vnc/Vnc.py
src/cpu/BaseCPU.py
src/cpu/CPUTracers.py
src/cpu/CheckerCPU.py
src/cpu/DummyChecker.py
src/cpu/InstPBTrace.py
src/cpu/kvm/BaseKvmCPU.py
src/cpu/kvm/X86KvmCPU.py
src/cpu/minor/MinorCPU.py
src/cpu/o3/FUPool.py
src/cpu/o3/FuncUnitConfig.py
src/cpu/o3/O3CPU.py
src/cpu/o3/O3Checker.py
src/cpu/o3/probe/ElasticTrace.py
src/cpu/o3/probe/SimpleTrace.py
src/cpu/simple/AtomicSimpleCPU.py
src/cpu/simple/BaseSimpleCPU.py
src/cpu/simple/NonCachingSimpleCPU.py
src/cpu/simple/TimingSimpleCPU.py
src/cpu/simple/probes/SimPoint.py
src/cpu/testers/directedtest/RubyDirectedTester.py
src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
src/cpu/testers/memtest/MemTest.py
src/cpu/testers/rubytest/RubyTester.py
src/cpu/testers/traffic_gen/BaseTrafficGen.py
src/cpu/testers/traffic_gen/PyTrafficGen.py
src/cpu/testers/traffic_gen/TrafficGen.py
src/cpu/trace/TraceCPU.py
src/dev/BadDevice.py
src/dev/Device.py
src/dev/Platform.py
src/dev/alpha/AlphaBackdoor.py
src/dev/alpha/Tsunami.py
src/dev/arm/EnergyCtrl.py
src/dev/arm/FlashDevice.py
src/dev/arm/Gic.py
src/dev/arm/NoMali.py
src/dev/arm/RealView.py
src/dev/arm/UFSHostDevice.py
src/dev/arm/VirtIOMMIO.py
src/dev/i2c/I2C.py
src/dev/mips/Malta.py
src/dev/net/Ethernet.py
src/dev/pci/CopyEngine.py
src/dev/pci/PciDevice.py
src/dev/pci/PciHost.py
src/dev/serial/Terminal.py
src/dev/serial/Uart.py
src/dev/sparc/T1000.py
src/dev/storage/Ide.py
src/dev/virtio/VirtIO.py
src/dev/virtio/VirtIO9P.py
src/dev/virtio/VirtIOBlock.py
src/dev/virtio/VirtIOConsole.py
src/dev/x86/Cmos.py
src/dev/x86/I8042.py
src/dev/x86/I82094AA.py
src/dev/x86/I8237.py
src/dev/x86/I8254.py
src/dev/x86/I8259.py
src/dev/x86/Pc.py
src/dev/x86/PcSpeaker.py
src/dev/x86/SouthBridge.py
src/gpu-compute/GPU.py
src/gpu-compute/LdsState.py
src/learning_gem5/part2/SimpleCache.py
src/learning_gem5/part2/SimpleMemobj.py
src/mem/AbstractMemory.py
src/mem/AddrMapper.py
src/mem/Bridge.py
src/mem/CommMonitor.py
src/mem/DRAMCtrl.py
src/mem/ExternalMaster.py
src/mem/ExternalSlave.py
src/mem/HMCController.py
src/mem/MemChecker.py
src/mem/MemDelay.py
src/mem/MemObject.py
src/mem/SerialLink.py
src/mem/SimpleMemory.py
src/mem/XBar.py
src/mem/cache/Cache.py
src/mem/cache/prefetch/Prefetcher.py
src/mem/cache/tags/Tags.py
src/mem/probes/MemFootprintProbe.py
src/mem/probes/MemTraceProbe.py
src/mem/probes/StackDistProbe.py
src/mem/qos/QoSMemCtrl.py
src/mem/qos/QoSMemSinkCtrl.py
src/mem/ruby/network/BasicRouter.py
src/mem/ruby/network/Network.py
src/mem/ruby/network/garnet2.0/GarnetLink.py
src/mem/ruby/network/garnet2.0/GarnetNetwork.py
src/mem/ruby/network/simple/SimpleLink.py
src/mem/ruby/network/simple/SimpleNetwork.py
src/mem/ruby/slicc_interface/Controller.py
src/mem/ruby/structures/LRUReplacementPolicy.py
src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
src/mem/ruby/structures/RubyCache.py
src/mem/ruby/structures/RubyPrefetcher.py
src/mem/ruby/system/GPUCoalescer.py
src/mem/ruby/system/RubySystem.py
src/mem/ruby/system/Sequencer.py
src/mem/ruby/system/VIPERCoalescer.py
src/mem/ruby/system/WeightedLRUReplacementPolicy.py
src/mem/slicc/symbols/StateMachine.py
src/sim/System.py
src/sim/TickedObject.py
src/sim/power/MathExprPowerModel.py
src/sim/power/ThermalModel.py