back.rtlil: explicitly set the top module.
authorwhitequark <cz@m-labs.hk>
Thu, 13 Dec 2018 03:50:04 +0000 (03:50 +0000)
committerwhitequark <cz@m-labs.hk>
Thu, 13 Dec 2018 03:50:04 +0000 (03:50 +0000)
commitefdd2206c894e1c075e17d6eda300d5776238348
tree8404601edc5cd759b8429bc9d4c6e2d5b774dedb
parentd19b28f23f336adf4095a72e36a07d68bfcc0927
back.rtlil: explicitly set the top module.
nmigen/back/rtlil.py