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(parent: 8e2690a) | patch
back.rtlil: do not translate empty fragments.
authorwhitequark <cz@m-labs.hk>
Sun, 23 Dec 2018 09:20:02 +0000 (09:20 +0000)
committerwhitequark <cz@m-labs.hk>
Sun, 23 Dec 2018 09:20:02 +0000 (09:20 +0000)
commiteffc41f14003a86481f383d00a9009135f59156e
tree556b6b3e3a9e8f77890adaa82b671f0b8ab8a485tree
parent8e2690af264ea29d97dd81a8bbb7db37aa8d6d97commit | diff
back.rtlil: do not translate empty fragments.

The resulting Verilog confuses some frontends.
nmigen/back/rtlil.py diff | blob | history