Closes #1717. Add more precise Verilog source location information to AST and RTLIL...
authorAlberto Gonzalez <boqwxp@airmail.cc>
Sun, 23 Feb 2020 07:19:52 +0000 (07:19 +0000)
committerAlberto Gonzalez <boqwxp@airmail.cc>
Sun, 23 Feb 2020 07:22:26 +0000 (07:22 +0000)
commitf0afd65035fefebdea8edbd00c916c5f33e8a634
tree5d34c5920dc230388c41bb7380e1241dec274fcf
parent6edca05793197a846bbfb0329e836c87fa5aabb6
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
frontends/ast/ast.cc
frontends/ast/ast.h
frontends/ast/genrtlil.cc
frontends/ast/simplify.cc
frontends/verilog/verilog_frontend.cc
frontends/verilog/verilog_frontend.h
frontends/verilog/verilog_lexer.l
frontends/verilog/verilog_parser.y
kernel/rtlil.cc