projects / gem5.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 2775f55) | patch
riscv: Get rid of ISA specific register types in Interrupts.
authorAustin Harris <austinharris@utexas.edu>
Mon, 4 Feb 2019 23:48:52 +0000 (17:48 -0600)
committerAustin Harris <austin.dane.harris@gmail.com>
Tue, 5 Feb 2019 00:09:42 +0000 (00:09 +0000)
commitf0e2caf84fbbf225e46cbda61e45fc5727d4d885
tree946257111d4f66a90b768e79b24c99b622e8c174tree
parent2775f55447edb344d99f30273ad93fea515d7e2bcommit | diff
riscv: Get rid of ISA specific register types in Interrupts.

Change-Id: I5542649c6af27a286f276a289b86c40dd7e32abc
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/16122
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
src/arch/riscv/interrupts.hh diff | blob | history