SystemVerilog also has assume(), added implicit -D FORMAL
authorClifford Wolf <clifford@clifford.at>
Tue, 13 Oct 2015 12:21:20 +0000 (14:21 +0200)
committerClifford Wolf <clifford@clifford.at>
Tue, 13 Oct 2015 12:21:20 +0000 (14:21 +0200)
commitf13e3873212fb4338ee3dd180cb9b0cd3d134935
treef2cfe06b4332859abb143fe4ed69f054de491522
parent34f34be17c891ffb99ca76700634aeff9da76bde
SystemVerilog also has assume(), added implicit -D FORMAL
frontends/verilog/preproc.cc
frontends/verilog/verilog_frontend.cc
frontends/verilog/verilog_lexer.l