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re PR target/16176 (Miscompilation of unaligned data in MIPS backend (SB1 flavor))
authorRichard Sandiford <rsandifo@redhat.com>
Fri, 25 Jun 2004 18:24:51 +0000 (18:24 +0000)
committerRichard Sandiford <rsandifo@gcc.gnu.org>
Fri, 25 Jun 2004 18:24:51 +0000 (18:24 +0000)
commitf1526aaae77c8082ef42691d03254926f5104b64
tree4761c6694179d05866b445599129f1c8450da5fctree
parent2fbe90f22457f0a82c1d10ff5a918259c41859b1commit | diff
re PR target/16176 (Miscompilation of unaligned data in MIPS backend (SB1 flavor))

PR target/16176
* config/mips/mips.c (mips_expand_unaligned_load): Use a temporary
register for the destination of the lwl or ldl.

From-SVN: r83668
gcc/ChangeLog diff | blob | history
gcc/config/mips/mips.c diff | blob | history
gcc/testsuite/ChangeLog diff | blob | history
gcc/testsuite/gcc.c-torture/execute/20040625-1.c [new file with mode: 0644] blob