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(parent: ca6e768) | patch
back.rtlil: more consistent prefixing for subfragment port wires.
authorwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 04:21:11 +0000 (04:21 +0000)
committerwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 04:21:11 +0000 (04:21 +0000)
commitf1f70a8990b4cbc274d272f28a1714b613260b4f
tree22867d0e02f4f5191da2fc1bdb3c5b1e5f0e826etree
parentca6e768dd8cd3799442bf027f215c139a01c764acommit | diff
back.rtlil: more consistent prefixing for subfragment port wires.
nmigen/back/rtlil.py diff | blob | history