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(parent: 37531ce) | patch
Add system Verilog support for the Vivado builder
authorMartin Cornil <martin.cornil@railnova.eu>
Thu, 10 Oct 2019 12:06:37 +0000 (14:06 +0200)
committerMartin Cornil <martin.cornil@railnova.eu>
Thu, 10 Oct 2019 12:10:28 +0000 (14:10 +0200)
commitf2369a4c9eeb19862dcae538d6d7f72148070a66
treed7ac176cce128ee53d489116f7cd43beb7e410ddtree
parent37531cec810a2fb72ab78dafe2d93b02c64f9eb4commit | diff
Add system Verilog support for the Vivado builder
litex/build/generic_platform.py diff | blob | history
litex/build/tools.py diff | blob | history
litex/build/xilinx/vivado.py diff | blob | history