mem: Split port retry for all different packet classes
authorAndreas Hansson <andreas.hansson@arm.com>
Mon, 2 Mar 2015 09:00:35 +0000 (04:00 -0500)
committerAndreas Hansson <andreas.hansson@arm.com>
Mon, 2 Mar 2015 09:00:35 +0000 (04:00 -0500)
commitf26a28929583f2ed7fb55521e49c3f9bef557c05
treee5d71fc69566b02a394015776b0f3f4e3be81427
parent6ebe8d863ae0c5a7799e9421da32593ac35e1cc7
mem: Split port retry for all different packet classes

This patch fixes a long-standing isue with the port flow
control. Before this patch the retry mechanism was shared between all
different packet classes. As a result, a snoop response could get
stuck behind a request waiting for a retry, even if the send/recv
functions were split. This caused message-dependent deadlocks in
stress-test scenarios.

The patch splits the retry into one per packet (message) class. Thus,
sendTimingReq has a corresponding recvReqRetry, sendTimingResp has
recvRespRetry etc. Most of the changes to the code involve simply
clarifying what type of request a specific object was accepting.

The biggest change in functionality is in the cache downstream packet
queue, facing the memory. This queue was shared by requests and snoop
responses, and it is now split into two queues, each with their own
flow control, but the same physical MasterPort. These changes fixes
the previously seen deadlocks.
67 files changed:
src/arch/x86/pagetable_walker.cc
src/arch/x86/pagetable_walker.hh
src/cpu/kvm/base.hh
src/cpu/minor/fetch1.cc
src/cpu/minor/fetch1.hh
src/cpu/minor/lsq.cc
src/cpu/minor/lsq.hh
src/cpu/o3/cpu.cc
src/cpu/o3/cpu.hh
src/cpu/o3/fetch.hh
src/cpu/o3/fetch_impl.hh
src/cpu/o3/lsq.hh
src/cpu/o3/lsq_impl.hh
src/cpu/simple/atomic.hh
src/cpu/simple/timing.cc
src/cpu/simple/timing.hh
src/cpu/testers/directedtest/RubyDirectedTester.hh
src/cpu/testers/memtest/memtest.cc
src/cpu/testers/memtest/memtest.hh
src/cpu/testers/networktest/networktest.cc
src/cpu/testers/networktest/networktest.hh
src/cpu/testers/rubytest/RubyTester.hh
src/cpu/testers/traffic_gen/traffic_gen.cc
src/cpu/testers/traffic_gen/traffic_gen.hh
src/dev/dma_device.cc
src/dev/dma_device.hh
src/mem/addr_mapper.cc
src/mem/addr_mapper.hh
src/mem/bridge.cc
src/mem/bridge.hh
src/mem/cache/base.cc
src/mem/cache/base.hh
src/mem/cache/cache.hh
src/mem/cache/cache_impl.hh
src/mem/coherent_xbar.cc
src/mem/coherent_xbar.hh
src/mem/comm_monitor.cc
src/mem/comm_monitor.hh
src/mem/dram_ctrl.cc
src/mem/dram_ctrl.hh
src/mem/dramsim2.cc
src/mem/dramsim2.hh
src/mem/external_slave.cc
src/mem/mem_checker_monitor.cc
src/mem/mem_checker_monitor.hh
src/mem/mport.hh
src/mem/noncoherent_xbar.cc
src/mem/noncoherent_xbar.hh
src/mem/packet_queue.cc
src/mem/packet_queue.hh
src/mem/port.cc
src/mem/port.hh
src/mem/qport.hh
src/mem/ruby/slicc_interface/AbstractController.cc
src/mem/ruby/slicc_interface/AbstractController.hh
src/mem/ruby/structures/RubyMemoryControl.hh
src/mem/ruby/system/DMASequencer.cc
src/mem/ruby/system/DMASequencer.hh
src/mem/ruby/system/RubyPort.cc
src/mem/ruby/system/RubyPort.hh
src/mem/simple_mem.cc
src/mem/simple_mem.hh
src/mem/tport.cc
src/mem/tport.hh
src/mem/xbar.cc
src/mem/xbar.hh
src/sim/system.hh