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re PR target/78192 (extract from vector registers to int results in wrong data order)
authorMichael Meissner <meissner@linux.vnet.ibm.com>
Thu, 3 Nov 2016 23:32:07 +0000 (23:32 +0000)
committerMichael Meissner <meissner@gcc.gnu.org>
Thu, 3 Nov 2016 23:32:07 +0000 (23:32 +0000)
commitf2834ebc00d847dcac85c44640a2c7fb2cdd340e
treec9942ab81dd9456b420d9c144bde4c23c85ee2bftree
parent0bc36dec0f6a5d73b79e78c549533261b76602eccommit | diff
re PR target/78192 (extract from vector registers to int results in wrong data order)

2016-11-03  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/78192
* config/rs6000/vsx.md (vsx_extract_<mode>_di): The element number
has already been adjusted for endianness, so don't adjust it any
further.

From-SVN: r241834
gcc/ChangeLog diff | blob | history
gcc/config/rs6000/vsx.md diff | blob | history