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(parent: dcc881d) | patch
soc: Don't create a wishbone slave to LiteDRAM with no CPU
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 12 May 2020 11:30:19 +0000 (21:30 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 12 May 2020 11:30:19 +0000 (21:30 +1000)
commitf28f2471303349e886b3636a0f55d7d533c3c084
treeab29e40338fb4b65e10db2c6602741173e7c7f8btree
parentdcc881db924370d8aba828e7a3a4990211723eb7commit | diff
soc: Don't create a wishbone slave to LiteDRAM with no CPU

When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
litex/soc/integration/soc.py diff | blob | history