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(parent: 092f0cb) | patch
sv: fix up end label checking
authorZachary Snow <zach@zachjs.com>
Mon, 14 Jun 2021 19:32:01 +0000 (15:32 -0400)
committerZachary Snow <zachary.j.snow@gmail.com>
Thu, 17 Jun 2021 01:48:05 +0000 (21:48 -0400)
commitf2c2d73f36d7aaef90ded549143d1ee0c4d4a9f5
treed7f7afbb2dd1662c77ba1075a4f8ba6d2055cd03tree
parent092f0cb01e91b65d5ecc7c8e45f0eefa30b8c205commit | diff
sv: fix up end label checking

- disallow [gen]blocks with an end label but not begin label
- check validity of module end label
- fix memory leak of package name and end label
- fix memory leak of module end label
frontends/verilog/verilog_parser.y diff | blob | history
tests/simple/matching_end_labels.sv [new file with mode: 0644] blob
tests/verilog/block_end_label_only.ys [new file with mode: 0644] blob
tests/verilog/block_end_label_wrong.ys [new file with mode: 0644] blob
tests/verilog/gen_block_end_label_only.ys [new file with mode: 0644] blob
tests/verilog/gen_block_end_label_wrong.ys [new file with mode: 0644] blob
tests/verilog/module_end_label.ys [new file with mode: 0644] blob