i965/blorp: Use 16 pixel dispatch on Gen7.
authorPaul Berry <stereotype441@gmail.com>
Thu, 10 May 2012 00:14:56 +0000 (17:14 -0700)
committerPaul Berry <stereotype441@gmail.com>
Fri, 25 May 2012 15:45:11 +0000 (08:45 -0700)
commitf2cdfa4c8522b6b0f5d1b0a6c42ed39e0d47c876
tree15b22fe4475494f4a52d6f26979096901e50afec
parentf7df7917e050b90df69c888e1f2ea0482ddd6b1d
i965/blorp: Use 16 pixel dispatch on Gen7.

Gen7 hardware requires us to enable at least one WM dispatch mode,
even if there is no program being dispatched to.  When this code was
only used for HiZ operations (which don't use a WM program), we used
32-pixel dispatch, because it didn't matter.  But blit programs are
compiled for 16-pixel dispatch.  So just enable 16-wide dispatch
unconditionally.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
v2: Enable 16-wide dispatch unconditionally rather than add the
unnecessary complication of using 32-wide dispatch when there is no WM
program.
src/mesa/drivers/dri/i965/gen7_blorp.cpp