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i965/vec4: Don't coalesce regs in Gen6 MATH ops if reswizzle/writemask needed
authorAntia Puentes <apuentes@igalia.com>
Tue, 22 Sep 2015 16:17:45 +0000 (18:17 +0200)
committerAntia Puentes <apuentes@igalia.com>
Wed, 23 Sep 2015 11:12:25 +0000 (13:12 +0200)
commitf2e75ac88a92ab2180de576aca298929cfce03f2
tree073295cf1e47911daeabc9ee80b65342d18d0d78tree
parentcf439951b791827677e96d29e209b5fc08d07a2ecommit | diff
i965/vec4: Don't coalesce regs in Gen6 MATH ops if reswizzle/writemask needed

Gen6 MATH instructions can not execute in align16 mode, so swizzles or
writemasking are not allowed.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92033
Reviewed-by: Matt Turner <mattst88@gmail.com>
src/mesa/drivers/dri/i965/brw_ir_vec4.h diff | blob | history
src/mesa/drivers/dri/i965/brw_vec4.cpp diff | blob | history