Merge pull request #1386 from YosysHQ/clifford/fix1360
authorClifford Wolf <clifford@clifford.at>
Fri, 20 Sep 2019 11:30:28 +0000 (13:30 +0200)
committerGitHub <noreply@github.com>
Fri, 20 Sep 2019 11:30:28 +0000 (13:30 +0200)
commitf3781f98db227f160e08b2fc7cf8c61f663a56c9
tree7d16d0a2c04b9aead04e7f46253e2b35a4e4b309
parentc072e00a393319f3ff338291798f52038eda11fe
parent8da0888bf6ae4c975c6d3b0c9a656bc10e1283e4
Merge pull request #1386 from YosysHQ/clifford/fix1360

Fix handling of read_verilog config in AstModule::reprocess_module()