Merge pull request #729 from whitequark/write_verilog_initial
authorClifford Wolf <clifford@clifford.at>
Sun, 16 Dec 2018 14:50:16 +0000 (15:50 +0100)
committerGitHub <noreply@github.com>
Sun, 16 Dec 2018 14:50:16 +0000 (15:50 +0100)
commitf481ad4d448611467a43b1a2f55980914cc1a701
tree46f260e34db488814bff43f3f370a9c39c889d23
parent0c69f1d7770a7afc6c07d3fb0adaa8d5548e4f27
parent7fe770a441a129c509fd4da04b60ada942a28bc8
Merge pull request #729 from whitequark/write_verilog_initial

write_verilog: correctly map RTLIL `sync init`