projects / yosys.git / commit
| author | Marcelina Kościelnicka <mwk@0x04.net> | |
| Sun, 27 Feb 2022 08:57:10 +0000 (09:57 +0100) | ||
| committer | Marcelina Kościelnicka <mwk@0x04.net> | |
| Wed, 18 May 2022 15:32:56 +0000 (17:32 +0200) | ||
| commit | f4d1426229e0843d55a7ac2a10760acecf9c6710 | |
| tree | 7912276260474807286ed98c7516f05a7dba0c28 | tree |
| parent | d7dc2313b915d3c316630104a86eb754744fdd57 | commit | diff |
| techlibs/anlogic/.gitignore | [deleted file] | blob | history |
| techlibs/anlogic/Makefile.inc | diff | blob | history | |
| techlibs/anlogic/brams.txt | diff | blob | history | |
| techlibs/anlogic/brams_init.py | [deleted file] | blob | history |
| techlibs/anlogic/brams_map.v | diff | blob | history | |
| techlibs/anlogic/lutram_init_16x4.vh | [deleted file] | blob | history |
| techlibs/anlogic/lutrams.txt | diff | blob | history | |
| techlibs/anlogic/lutrams_map.v | diff | blob | history | |
| techlibs/anlogic/synth_anlogic.cc | diff | blob | history |