Merge pull request #834 from YosysHQ/clifford/siminit
authorClifford Wolf <clifford@clifford.at>
Thu, 28 Feb 2019 23:03:55 +0000 (15:03 -0800)
committerGitHub <noreply@github.com>
Thu, 28 Feb 2019 23:03:55 +0000 (15:03 -0800)
commitf505a41b7606c89289348d4c90a8ff85b3ede19a
tree125c3b702ca30880f6639395ed024d5eac77b2b3
parente2fc18f27b5e9f506724a486787c2106b9f7fb4f
parent241901461ae02c6a41837e254088f277b8167476
Merge pull request #834 from YosysHQ/clifford/siminit

Add "write_verilog -siminit"