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(parent: 0ef1d44) | patch
gen/sim: hack to update vcd output file during simulation (allow visualizing progress...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 25 Mar 2016 12:08:39 +0000 (13:08 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 25 Mar 2016 12:22:26 +0000 (13:22 +0100)
commitf512971d9e84ea56b39a87bf0621e5a347048c21
tree11ab790271966a72140c209cf46e5fcb7cbb32d4tree
parent0ef1d44c4481bc559c4edcb147b829974d8eb6f3commit | diff
gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop)
litex/gen/sim/core.py diff | blob | history
litex/gen/sim/vcd.py diff | blob | history