fhdl/verilog: fix case value sort
authorSebastien Bourdeauducq <sb@m-labs.hk>
Thu, 17 Sep 2015 00:03:48 +0000 (08:03 +0800)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Thu, 17 Sep 2015 00:03:48 +0000 (08:03 +0800)
commitf5ab734bdf24cb56545d3d21649e7bf64eb09ac5
treecdd5d1274ebba86da12429cadf72fc8bdb460bee
parente940c6d9b9aa126a1eb9d8376a9ea3ce2bdfa1b7
fhdl/verilog: fix case value sort
migen/fhdl/verilog.py