WB2CSR: Use CSR address_width for the wishbone bus
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 12 May 2020 11:37:36 +0000 (21:37 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 12 May 2020 11:37:36 +0000 (21:37 +1000)
commitf628ff6b47d90c783c60bbada5abbf7bc0fc6660
treeba0f16e26d6a32899a530e3c76a8b4d6ea5512dd
parent520c17e96d6fcba23de9435bc6f38379da09d7ec
WB2CSR: Use CSR address_width for the wishbone bus

Currently, we create a wishbone interface with the default address
width (30 bits) for the bridge. Instead, create an interface that
has the same number of address bits as the CSR bus.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
litex/soc/interconnect/wishbone2csr.py