git.libre-soc.org Git - yosys.git/commit

author	Clifford Wolf <clifford@clifford.at>
	Fri, 19 Aug 2016 16:38:25 +0000 (18:38 +0200)
committer	Clifford Wolf <clifford@clifford.at>
	Fri, 19 Aug 2016 16:38:25 +0000 (18:38 +0200)
commit	f6629b9c29838879cec6a94d6cb47afc6fbd2db4
tree	a75ca899efb7a6d8889fada7a35e298521174457	tree
parent	9b8e06bee177f53c34a9dd6dd907a822f21659be	commit \| diff

Optimize memory address port width in wreduce and memory_collect, not verilog front-end

frontends/ast/genrtlil.cc		diff \| blob \| history
frontends/ast/simplify.cc		diff \| blob \| history
passes/memory/memory_collect.cc		diff \| blob \| history
passes/opt/wreduce.cc		diff \| blob \| history