interconnect: add bus/bank components from Migen
authorSebastien Bourdeauducq <sb@m-labs.hk>
Thu, 24 Sep 2015 12:48:18 +0000 (20:48 +0800)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Thu, 24 Sep 2015 12:48:18 +0000 (20:48 +0800)
commitf69674e89c9ace5e752c3bea4387067bf4a5b4a0
tree18411cae41eb4550c6a87d91a66bb5099ad84d2c
parentecdc4101b410b7e89ec54d428f5196e078bd5f08
interconnect: add bus/bank components from Migen
misoc/interconnect/__init__.py [new file with mode: 0644]
misoc/interconnect/csr.py [new file with mode: 0644]
misoc/interconnect/csr_bus.py [new file with mode: 0644]
misoc/interconnect/csr_eventmanager.py [new file with mode: 0644]
misoc/interconnect/lasmi_bus.py [new file with mode: 0644]
misoc/interconnect/lasmi_xbar.py [new file with mode: 0644]
misoc/interconnect/lasmibus.py [deleted file]
misoc/interconnect/lasmixbar.py [deleted file]
misoc/interconnect/wishbone.py [new file with mode: 0644]
misoc/interconnect/wishbone2csr.py [new file with mode: 0644]