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(parent: f98e916) | patch
make handling of interstage buffers (i.e. StageQueues) more consistent: (1)number...
authorKorey Sewell <ksewell@umich.edu>
Wed, 4 Mar 2009 18:17:07 +0000 (13:17 -0500)
committerKorey Sewell <ksewell@umich.edu>
Wed, 4 Mar 2009 18:17:07 +0000 (13:17 -0500)
commitf69b018571a6396d0e679d4d0eceb47ef4496530
tree00e8e6ad7b94e17a9ca328e37fb8bdbd5225cbf9tree
parentf98e9161a83cd9bafbe7e5612db344a8b5cb2ae1commit | diff
make handling of interstage buffers (i.e. StageQueues) more consistent: (1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads
src/cpu/inorder/cpu.cc diff | blob | history
src/cpu/inorder/first_stage.cc diff | blob | history
src/cpu/inorder/pipeline_stage.cc diff | blob | history
src/cpu/inorder/pipeline_stage.hh diff | blob | history