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(parent: 7ea0a59) | patch
Do not rename VHDL entities to "entity(impl)" when they are top modules
authorClifford Wolf <clifford@clifford.at>
Wed, 20 Nov 2019 11:54:10 +0000 (12:54 +0100)
committerClifford Wolf <clifford@clifford.at>
Wed, 20 Nov 2019 11:54:10 +0000 (12:54 +0100)
commitf6ff311a1dc9876911594328350e2d3fc62a5535
treea1a5aa06a6c361222c3a880c408b2d31ab691818tree
parent7ea0a5937ba2572f6d9d62e73e24df480c49561dcommit | diff
Do not rename VHDL entities to "entity(impl)" when they are top modules

Signed-off-by: Clifford Wolf <clifford@clifford.at>
frontends/verific/verific.cc diff | blob | history
frontends/verific/verific.h diff | blob | history