projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 7043e6a) | patch
mila: add clk_domain support
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 6 Oct 2014 08:24:21 +0000 (10:24 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 6 Oct 2014 10:07:20 +0000 (12:07 +0200)
commitf72f11f7b41ffaa7a966317e543182973a993ac8
treebd284542b16029a922637949ce50bc25fccb023ctree
parent7043e6a5f345bebe98a7d7da92c1b3076bd1b05ccommit | diff
mila: add clk_domain support

an AsyncFIFO is inserted when clk_domain is not "sys" to enable capture from another clock domain.
sys_clk frequency need to be greater than clk_domain clock.

future possible improvement: automatic insertion of a converter when clk_domain frequency is
greater than sys_clk.
miscope/mila.py diff | blob | history