add carry-roll-over-vector-mul-with-add (!) unit test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 29 Sep 2022 13:57:26 +0000 (14:57 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 29 Sep 2022 13:57:26 +0000 (14:57 +0100)
commitf7468f57cdabc5685feaf503f4a5f9b669a35de7
tree295d3079a179b6dac3a5ac36bb9d1b1bb186edf1
parentd67e1cb40fa22033fc57f66078a58b694df660bb
add carry-roll-over-vector-mul-with-add (!) unit test
test_caller_svp64_bigint.py
https://bugs.libre-soc.org/show_bug.cgi?id=937
src/openpower/decoder/isa/test_caller_svp64_bigint.py