build/sim: improve timebase calculation (strict checks) and update modules
authorJędrzej Boczar <jboczar@antmicro.com>
Tue, 4 Aug 2020 12:00:58 +0000 (14:00 +0200)
committerJędrzej Boczar <jboczar@antmicro.com>
Tue, 4 Aug 2020 12:00:58 +0000 (14:00 +0200)
commitf778ff09dcc0edcdbea34f41dc64c05b4dee1587
tree7e4e7133b0dbd5b4f60caefc855f2079289aff92
parentc1ae7e596c3e11db309659c8bfc197ebdeec14c5
build/sim: improve timebase calculation (strict checks) and update modules
12 files changed:
litex/build/sim/config.py
litex/build/sim/core/modules.h
litex/build/sim/core/modules/clocker/clocker.c
litex/build/sim/core/modules/ethernet/ethernet.c
litex/build/sim/core/modules/jtagremote/jtagremote.c
litex/build/sim/core/modules/serial2console/serial2console.c
litex/build/sim/core/modules/serial2tcp/serial2tcp.c
litex/build/sim/core/modules/spdeeprom/spdeeprom.c
litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c
litex/build/sim/core/sim.c
litex/build/sim/core/veril.cpp
litex/build/sim/core/veril.h