core: Double the dcache and icache sizes
authorPaul Mackerras <paulus@ozlabs.org>
Wed, 3 Jun 2020 01:26:33 +0000 (11:26 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Sat, 13 Jun 2020 10:07:56 +0000 (20:07 +1000)
commitf80da65799c366edb88e20ec4f95f60c62ac3d94
tree7441a04d5ae6eff47050eb6c9fd7f45a2dff8e9a
parentb5a7dbb78dff640ee18b6662ea007a946a4ebb09
core: Double the dcache and icache sizes

This makes the dcache and icache both be 8kB.  This still only uses
one BRAM per way per cache on the Artix-7, since the BRAMs were only
half-used previously.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
core.vhdl