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(parent: 56bb42a) | patch
back.rtlil: infer bit width for instance parameters.
authorwhitequark <whitequark@whitequark.org>
Wed, 27 Nov 2019 17:58:42 +0000 (17:58 +0000)
committerwhitequark <whitequark@whitequark.org>
Wed, 27 Nov 2019 17:58:42 +0000 (17:58 +0000)
commitf8428ff5051c2c7295e93a0a191880076b5dffab
tree24102d3349eb30d87eb66383183ec313492a55d1tree
parent56bb42aff27914dc88ae0fdee9891a7aa5004229commit | diff
back.rtlil: infer bit width for instance parameters.

Otherwise, Yosys assumes it is always 32, which is often
inappropriate.
nmigen/back/rtlil.py diff | blob | history