projects / openpower-isa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 4f52c16) | patch
argh, extremely annoying: 4-operand dsld/dsrd is not possible to
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 22 Oct 2022 16:32:41 +0000 (17:32 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:15 +0000 (19:51 +0100)
commitf843a7d2831361c293f4af11e85fb360895f4269
tree45aa199d2a36d682043931df6a91de90600f2414tree
parent4f52c161c561a42ac0920ba5e656007a28e7acbfcommit | diff
argh, extremely annoying: 4-operand dsld/dsrd is not possible to
have EXTRA3, therefore it fails as a bigint operation. reverting
openpower/isa/svfixedarith.mdwn diff | blob | history
openpower/isatables/RM-1P-2S1D.csv diff | blob | history
openpower/isatables/RM-1P-3S1D.csv diff | blob | history
openpower/isatables/fields.text diff | blob | history
openpower/isatables/minor_31.csv diff | blob | history
openpower/isatables/minor_4.csv diff | blob | history
src/openpower/sv/trans/svp64.py diff | blob | history
src/openpower/sv/trans/test_pysvp64dis.py diff | blob | history
src/openpower/test/bigint/bigint_cases.py diff | blob | history