mem: Align cache behaviour in atomic when upstream is responding
authorAndreas Hansson <andreas.hansson@arm.com>
Wed, 10 Feb 2016 09:08:24 +0000 (04:08 -0500)
committerAndreas Hansson <andreas.hansson@arm.com>
Wed, 10 Feb 2016 09:08:24 +0000 (04:08 -0500)
commitf84ee031ccdb63d016c6f55b578085a2e5af4a4b
tree3c494751302b00722e189fc9e9a2aabd76dfb492
parent986214f1816be2dc6f3758c4b80d8fbc945495b0
mem: Align cache behaviour in atomic when upstream is responding

Adopt the same flow as in timing mode, where the caches on the path to
memory get to keep the line (if present), and we use the
responderHadWritable flag to determine if we need to forward the
(invalidating) packet or not.
src/mem/cache/cache.cc