RISC-V: Add `OP_V' to .insn named opcodes
authorTsukasa OI <research_trasio@irq.a4lg.com>
Thu, 28 Jul 2022 13:02:05 +0000 (22:02 +0900)
committerNelson Chu <nelson.chu@sifive.com>
Fri, 29 Jul 2022 01:16:02 +0000 (09:16 +0800)
commitf8ad70a17bfc12199cc5a20b55b369c3dfa6cb42
tree9b1044270b75384ec9fd51a0b9c5483a14b1424d
parentd17823bfd35adb4caf3724512c3cd40a5a66402e
RISC-V: Add `OP_V' to .insn named opcodes

This commit adds `OP_V' (OP-V: vector instruction opcode for now
ratified `V' extension) to .insn opcode name list.  Although vector
instruction encoding is not implemented in `.insn' directive, it will
help future implementation of custom vector `.insn'.

gas/ChangeLog:

* config/tc-riscv.c (opcode_name_list): Add `OP_V'.
* testsuite/gas/riscv/insn.s: Add testcase.
* testsuite/gas/riscv/insn.d: Likewise.
* testsuite/gas/riscv/insn-dwarf.d: Reflect insn.s update.
gas/config/tc-riscv.c
gas/testsuite/gas/riscv/insn-dwarf.d
gas/testsuite/gas/riscv/insn.d
gas/testsuite/gas/riscv/insn.s