projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: f883f0c) | patch
Revert "gen/fhdl/verilog: allow single element verilog inline attribute"
authorArnaud Durand <arnaud.durand@unifr.ch>
Thu, 19 Dec 2019 07:53:44 +0000 (08:53 +0100)
committerArnaud Durand <arnaud.durand@unifr.ch>
Thu, 19 Dec 2019 07:53:44 +0000 (08:53 +0100)
commitf8c58216580e223558b539fa3f9a0a6969bdf9a3
tree7b24afe409a735e2cf96b2680178737d4604d34btree
parentf883f0c703792a53a7bad5b1f68ab24e712ad6c3commit | diff
Revert "gen/fhdl/verilog: allow single element verilog inline attribute"

This reverts commit b845755995a8517d8e0ffa86156fb5577201f7d4.
litex/build/lattice/diamond.py diff | blob | history
litex/gen/fhdl/verilog.py diff | blob | history