Refactoring: Renamed RTLIL::Module::wires to wires_
authorClifford Wolf <clifford@clifford.at>
Sat, 26 Jul 2014 23:49:51 +0000 (01:49 +0200)
committerClifford Wolf <clifford@clifford.at>
Sat, 26 Jul 2014 23:49:51 +0000 (01:49 +0200)
commitf9946232adf887e5aa4a48c64f88eaa17e424009
tree39594b3287c3369752668456c4a6b1735fb66e77
parentd7916a49aff3c47b7c1ce07abe3b6e3d5714079b
Refactoring: Renamed RTLIL::Module::wires to wires_
50 files changed:
backends/autotest/autotest.cc
backends/blif/blif.cc
backends/btor/btor.cc
backends/edif/edif.cc
backends/ilang/ilang_backend.cc
backends/intersynth/intersynth.cc
backends/spice/spice.cc
backends/verilog/verilog_backend.cc
frontends/ast/genrtlil.cc
frontends/liberty/liberty.cc
kernel/celltypes.h
kernel/driver.cc
kernel/modwalker.h
kernel/rtlil.cc
kernel/rtlil.h
manual/CHAPTER_Prog/stubnets.cc
manual/PRESENTATION_Prog/my_cmd.cc
passes/abc/abc.cc
passes/abc/blifparse.cc
passes/cmds/add.cc
passes/cmds/delete.cc
passes/cmds/rename.cc
passes/cmds/scc.cc
passes/cmds/select.cc
passes/cmds/setattr.cc
passes/cmds/setundef.cc
passes/cmds/show.cc
passes/cmds/splice.cc
passes/cmds/splitnets.cc
passes/cmds/stat.cc
passes/fsm/fsm_detect.cc
passes/fsm/fsm_extract.cc
passes/hierarchy/hierarchy.cc
passes/hierarchy/submod.cc
passes/memory/memory_map.cc
passes/memory/memory_share.cc
passes/opt/opt_clean.cc
passes/opt/opt_const.cc
passes/opt/opt_muxtree.cc
passes/opt/opt_rmdff.cc
passes/opt/opt_share.cc
passes/proc/proc_arst.cc
passes/sat/eval.cc
passes/sat/expose.cc
passes/sat/freduce.cc
passes/sat/miter.cc
passes/sat/sat.cc
passes/techmap/extract.cc
passes/techmap/iopadmap.cc
passes/techmap/techmap.cc