arch-arm: Implementation of Hardware Breakpoint exception

arch-arm: Implementation of Hardware Breakpoint exception

This code implementes hardware breakpoint exception as part of
software debug explained in ARMv8 reference manual ChapterD2.

+ ArmISA.py: Modify register to allow up to 15 Breakpoint registers
+ Sconscript: Add new file self_debug
+ faults.cc/hh: Defintion and implementation of HardwareBreakpoint
                exception inheriting ArmFault.
+ isa.cc/hh: ArmISA contains now an attribute pointing to the SelfDebug
             object that will be used to be access SelfDebug infrastructure
             Added special cases for setMiscReg to cache debug enable bits.
+ miscregs.hh/cc: Definition and initialization of DBGDCn and DBGDVn
                  registers.
+ tlb.cc/hh: We include the access to check for breakpoint instruction as
             part of the tlb translation process, checking if it comes from a
             fetch in the itlb
+ types.hh: Definition of new bitwise register types.
+ utility.cc/hh: Definition and implementation of auxiliar functions for
                the selfDebug.
+ self_debug.hh/cc: Main files that include the implemenattion of
            breakpoint checks, selfdebug enable and auxiliar functions.

Change-Id: I0e2a4be7f778de560c512253a9148da61e3e7e7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27967
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>