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(parent: f73ffac) | patch
radeon/llvm: Fix encoding of V_CNDMASK_B32
authorTom Stellard <thomas.stellard@amd.com>
Fri, 31 Aug 2012 20:11:38 +0000 (16:11 -0400)
committerTom Stellard <thomas.stellard@amd.com>
Tue, 4 Sep 2012 18:21:10 +0000 (14:21 -0400)
commitf9fede884b7ace711ccf63152afdbdaf209edced
treef6a299809e87115eb037e3a85da382bc3a13c34ctree
parentf73ffacbf0c65ad843406af37aa35e9112bc8038commit | diff
radeon/llvm: Fix encoding of V_CNDMASK_B32

The CodeEmitter was not setting the VGPR bit for src0, because the
instruction definition had the VCC register in the src0 slot, instead of
the actual src0 register.  This has been fixed by moving the VCC
register to the end of the operand list.
src/gallium/drivers/radeon/SIISelLowering.cpp diff | blob | history
src/gallium/drivers/radeon/SIInstructions.td diff | blob | history