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(parent: 8a4841d) | patch
cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.
authorwhitequark <whitequark@whitequark.org>
Thu, 11 Jun 2020 12:42:37 +0000 (12:42 +0000)
committerwhitequark <whitequark@whitequark.org>
Thu, 11 Jun 2020 12:43:17 +0000 (12:43 +0000)
commitfa04b1967076d8a97bdd8802664fd2d1a2424be2
tree2b62e95fbd193ffff5d0ccaafd237f22947e3d12tree
parent8a4841d78690313a91af97e8c6d9aa3e65a3e491commit | diff
cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.
backends/cxxrtl/cxxrtl.h diff | blob | history
backends/cxxrtl/cxxrtl_backend.cc diff | blob | history
backends/cxxrtl/cxxrtl_capi.h diff | blob | history