gen/fhdl: add simulation Display, Finish support.

gen/fhdl: add simulation Display, Finish support.

In some simulation cases, it's easier to add debug traces directly in the code
than in the verilog/Migen testbench. This adds support for verilog $display in
Migen code.

Being able to terminate a simulation from the code is also useful, this also
add support for verilog $finish.